what in All Locations Alaska Alabama Arkansas Arizona California Colorado Connecticut District of Columbia Delaware Florida Georgia Hawaii Iowa Idaho Illinois Indiana Kansas Kentucky Louisiana Massachusetts Maryland Maine Michigan Minnesota Missouri Mississippi Montana North Carolina North Dakota Nebraska New Hampshire New Jersey New Mexico Nevada New York Ohio Oklahoma Oregon Pennsylvania Puerto Rico Rhode Island South Carolina South Dakota Tennessee Texas Utah Virginia Vermont Washington Wisconsin West Virginia Wyoming       Stacked Chip Scale Packages SCSP Intern Job Company - Medtronic Location -  Tempe, Arizona  US   Job Code - 80724 Position - Intern Job First Active on: Wednesday, January 18, 2012 Stacked Chip Scale Packages (SCSP) Intern Position Description 2nd Level Interconnect Flux Dipped Assembly of Reduced Bump Height Stacked Chip Scale Packages (SCSP) on thin substrates (i.e. Injectable Reveal / PLPS) supported with Integral Dam Stiffener (IDS) frames Position Responsibilities Assignment Objective(s): Development of SCSP 2nd Level Interconnect Assembly Attach Process under the following constraints: • Thin (< 0.020”) PWB as used on Injectable Reveal / PLPS • SCSP bump diameter = 200µm as used on Injectable Reveal / PLPS • IDS board support in lieu of thicker PWB core Flux dipping of SCSP to replace solder paste printing due to process restrictions caused by IDS frame Project Description (e.g., Cognition Cockpit Simulation Use) Responsible for the Development of SCSP 2nd Level Interconnect Assembly Attach Process with reduced bump heights on thin PWB’s using IDS frames Deliverables: • Work with SCSP component engineer to: o Become familiar with the SCSP package feature(s) and PWB specification limits and tolerances o Measure and Analyze actual SCSP component package feature and PWB dimensions and variation with primary focus on SCSP bump height and coplanarity and PWB flatness o • Work with Pick and Place Process Engineer to: o Obtain a basic understanding of the pick and place equipment and process o Understand PWB board handling and clamping process and associated equipment hardware and tooling design and limitations o Measure and Analyze current flux dip process capability based on current tooling sets (ie.flux plates) available • Provide SCSP package and PWB specification & tolerance limits and process recommendations o Take into consideration the interaction between the coplanarity of the SCSP and the PWB o Define flux film thickness specification limits and tolerances o Create applicable design rules Basic Qualifications Prerequisites/Skills Needed to be Successful: Engineering student – preferably majoring in Mechanical Engineerin Skills Gained/Developed • Hands on experience with 6-Sigma Methodologies (DMAIC, GR&R, etc.) • SMT / DCA Manufacturing Process experience • Process Development • Hands on with Automated Equipment • Capability analysis • Drawing dimensioning and tolerance Documentation / Reporting (ie. ETR, EQDMS, etc.) Desired/Preferred Qualifications Physical Job Requirements REQUIREMENTS - QUALIFICATIONS: Stacked Chip Scale Packages (SCSP) Intern See information above Apply to this job! View Company Jobs Free Career Test Your Resume on 75 Job Sites

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